Double Data Rate (DDR), Quad Data Rate (QDR) or even more complex data clocking schemes are becoming common in order to meet the high data bandwidth requirement of recent systems. The data source, e.g., a chip on a PCB, usually supplies source synchronous data/clock, where the data transition edges line up with the clock transition edges with certain amount of jitter specification. The data destination, e.g., another chip on the same PCB, cannot simply use the supplied clock to clock the supplied data because of the source synchronicity. For DDR scheme, the data destination usually needs to derive a quadrature clock that is shifted by ninety degrees from the supplied clock in order to clock the supplied data.
A typical approach used in the industry to derive a quadrature clock is to use a complex circuitry, such as a Delay Locked Loop (DLL). However, this approach entails the following implementation issues:
1. DLL is usually a high speed, precision analog circuit that needs to have its own quite and properly isolated power and ground supplies, which requires a plethora of intricate design and noise isolation considerations. Although a digital-counter-based type of DLL that is simpler to design does exist, such DLL can only operate at much lower speed.
2. DLL design requires the use of a voltage/current controlled delay element, which has frequency tuning range limitation. It is very challenging to get a voltage/current controlled delay element design to work across a wide range of frequency, especially across entire IC Process, Voltage and Temperature (PVT) range. Thus, DLL design tends to have a somewhat narrow frequency operating range.
3. DLL design is not portable across different IC processes. Significant redesign effort is required every time the IC process is changed, which consumes precious engineering resources.
4. Designing a DLL to work over the entire PVT range is technically challenging, especially in low cost digital CMOS IC processes where precision devices are not readily available.
5. Designing a DLL into a large digital chip requires very significant effort. As an example, integration of the DLL into the data clocking area of a large digital chip is a complex task requiring a lot of attention to ensure signal integrity. In addition, it requires a complex, mixed-digital analog design verification.
The above implementation issues translate into long design and verification cycle time, which may result in severe detrimental schedule and financial consequences.
In view of the above issues, what is needed is a system and method for generating a delayed clock signal of an input clock signal that addresses at least some of these issues.